The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2022

Filed:

Mar. 24, 2020
Applicant:

Cypress Semiconductor Corporation, San Jose, CA (US);

Inventors:

Krishnaswamy Ramkumar, San Jose, CA (US);

Venkatraman Prabhakar, Pleasanton, CA (US);

Vineet Agrawal, San Jose, CA (US);

Long Hinh, San Jose, CA (US);

Santanu Kumar Samanta, West Bengal, IN;

Ravindra Kapre, San Jose, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/56 (2006.01); G06N 3/063 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/16 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01); H01L 27/11524 (2017.01); H01L 27/11529 (2017.01); H01L 27/1157 (2017.01); H01L 27/11573 (2017.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/792 (2006.01);
U.S. Cl.
CPC ...
G11C 11/5671 (2013.01); G06N 3/0635 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/16 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/3445 (2013.01); G11C 16/3459 (2013.01); H01L 27/1157 (2013.01); H01L 27/11524 (2013.01); H01L 27/11529 (2013.01); H01L 27/11573 (2013.01); H01L 29/6659 (2013.01); H01L 29/66833 (2013.01); H01L 29/7833 (2013.01); H01L 29/7923 (2013.01);
Abstract

A semiconductor device that has a silicon-oxide-nitride-oxide-silicon (SONOS) based non-volatile memory (NVM) array including charge-trapping memory cells arranged in rows and columns and configured to store one of N×analog values. Each charge-trapping memory cells may include a memory transistor including an angled lightly doped drain (LDD) implant extends at least partly under an oxide-nitride-oxide (ONO) layer of the memory transistor. The ONO layer disposed within the memory transistor and over an adjacent isolation structure has the same elevation substantially.


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