The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2022

Filed:

Nov. 16, 2018
Applicant:

GM Global Technology Operations Llc, Detroit, MI (US);

Inventors:

Shige Wang, Northville, MI (US);

Wei Tong, Troy, MI (US);

Shuqing Zeng, Sterling Heights, MI (US);

Roman L. Millett, Clinton Township, MI (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06V 10/70 (2022.01); G06F 9/30 (2018.01); G06N 3/04 (2006.01); G06F 3/06 (2006.01); G06N 3/08 (2006.01); G05D 1/02 (2020.01);
U.S. Cl.
CPC ...
G06V 10/768 (2022.01); G06F 3/0604 (2013.01); G06F 3/0631 (2013.01); G06F 3/0673 (2013.01); G06F 9/30 (2013.01); G06N 3/04 (2013.01); G06N 3/08 (2013.01); G05D 1/0246 (2013.01);
Abstract

A signal processing system includes a central processing unit (CPU) in communication with an accelerator, and an instruction scheduler in communication with the accelerator. A first memory device including a first instruction set is configured to operate the accelerator, a second instruction set is configured to operate the CPU, and a second memory device is configured to receive a datafile. The accelerator includes a plurality of processing engines (PEs) and an instruction scheduler, the instruction set includes a plurality of operators, and the instruction scheduler is configured to implement the operators in the accelerator employing the PEs. The CPU employs the operators implemented in the accelerator to analyze the datafile to extract a feature therefrom.


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