The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 07, 2022
Filed:
Mar. 02, 2020
Applicant:
Panasonic Corporation, Osaka, JP;
Inventors:
Masayoshi Nakayama, Kyoto, JP;
Kazuyuki Kouno, Osaka, JP;
Yuriko Hayata, Osaka, JP;
Takashi Ono, Osaka, JP;
Reiji Mochida, Osaka, JP;
Assignee:
PANASONIC CORPORATION, Osaka, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 3/063 (2006.01); G11C 11/54 (2006.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
G06N 3/063 (2013.01); G11C 11/54 (2013.01); G11C 13/003 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01);
Abstract
A neural network computation circuit includes in-area multiple-word line selection circuits that are provided in one-to-one correspondence to a plurality of word line areas into which a plurality of word lines included in a memory array are logically divided. Each of the in-area multiple-word line selection circuits sets one or more word lines in a selected state or a non-selected state, and includes a first latch and a second latch provided for each word line.