The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2022

Filed:

Aug. 19, 2020
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Sharon Graif, Zichron Yaakov, IL;

Kishalay Haldar, Bangalore, IN;

Navdeep Mer, Bangalore, IN;

Viney Kumar, Bangalore, IN;

Sriharsha Chakka, Bangalore, IN;

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/42 (2006.01); G06F 13/40 (2006.01); G06F 13/374 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4291 (2013.01); G06F 13/374 (2013.01); G06F 13/409 (2013.01); G06F 13/4031 (2013.01); G06F 13/4068 (2013.01);
Abstract

The systems and methods for hang correction in a power management interface bus cause secondary master devices associated with the power management interface bus to utilize timers to determine if a master that won arbitration has asserted a clock signal within a predefined amount of time. If a timer for a secondary master device expires without a clock signal being asserted by the winning master, the secondary master will assume ownership of the bus and assert a clock signal. Priorities between secondary masters are created by using a master identification (MID) value assigned during bus enumeration to determine a timer value. By allowing the secondary masters to assume ownership after expiration of respective timers, bus ownership is maintained in the event that a winning master hangs and does not assert ownership.


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