The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2022

Filed:

May. 20, 2020
Applicant:

Nanjing University, Jiangsu, CN;

Inventors:

Wei Jiang, Jiangsu, CN;

Zhaobang Zeng, Jiangsu, CN;

Peiyan Zhao, Jiangsu, CN;

Assignee:

Nanjing University, Jiangsu, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/26 (2020.01); G02F 1/225 (2006.01); H04B 10/079 (2013.01); G02F 1/21 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2637 (2013.01); G02F 1/2257 (2013.01); H04B 10/07953 (2013.01); G02F 1/212 (2021.01); G02F 2202/105 (2013.01);
Abstract

The invention discloses a fabrication process variation analysis method of a silicon-based Mach-Zehnder electro-optic modulator. The method includes the following steps: (1) use the input reflection coefficient Sto characterize and quantify the reflection deviation characteristics of the driving signal on the traveling wave electrode; (2) measure and quantify the modulated signal characteristics of the silicon Mach-Zehnder electro-optic modulator. The modulated signal characteristics include transmission characteristics, vertical direction characteristics and horizontal direction characteristics; (3) Pearson correlation coefficient and partial correlation coefficient are introduced. By analyzing the value and variation trend of Pearson correlation coefficient and partial correlation coefficient, the relationship between the deviation of the driving signal reflection and the deviation of the modulated signal characteristics is analyzed. The method of the present invention can establish the relationship between fabrication process control and performance analysis at the device level, and help to develop device designs with better fabrication tolerances.


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