The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 31, 2022

Filed:

Dec. 04, 2020
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Sovan Ghosh, Paschim Medinipur, IN;

Minkle Eldho Paul, Bengaluru, IN;

Laxmi Vivek Tripurari, Hyderabad, IN;

Amal Kumar Kundu, Bengaluru, IN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/12 (2006.01); H03M 1/46 (2006.01); H03M 1/10 (2006.01); H03M 1/06 (2006.01); G11C 27/02 (2006.01); H03M 1/00 (2006.01);
U.S. Cl.
CPC ...
H03M 1/468 (2013.01); H03M 1/1047 (2013.01); H03M 1/124 (2013.01); H03M 1/462 (2013.01); G11C 27/02 (2013.01); H03M 1/00 (2013.01); H03M 1/06 (2013.01); H03M 1/1009 (2013.01); H03M 1/12 (2013.01);
Abstract

An analog-to-digital converter (ADC) circuit includes a signal input terminal, a sample-and-hold circuit, and a successive approximation register (SAR) ADC. The sample-and-hold circuit includes an input terminal coupled to the signal input terminal. The SAR ADC includes a comparator, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a first input terminal coupled to the signal input terminal, a second input terminal coupled to an output terminal of the sample-and-hold circuit, and an output terminal coupled to a first input terminal of the comparator. The second CDAC includes a first input terminal coupled to the signal input terminal, an output terminal coupled to a second input terminal of the comparator.


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