The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 31, 2022
Filed:
Jan. 07, 2020
No.24 Research Institute of China Electronics Technology Group Corporation, Chongqing, CN;
Chongqing Gigachip Technology Co. Ltd., Chongqing, CN;
Yong Zhang, Chongqing, CN;
Ting Li, Chongqing, CN;
Zhengbo Huang, Chongqing, CN;
Yabo Ni, Chongqing, CN;
Dongbing Fu, Chongqing, CN;
NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION, Chongqing, CN;
CHONGQING GIGACHIP TECHNOLOGY CO. LTD., Chongqing, CN;
Abstract
An error extraction method for foreground digital correction of a pipeline analog-to-digital converter including: acquiring a transmission curve of a pipeline analog-to-digital converter, and controlling an input signal to be within a sub-segment 0 of the transmission curve; during extraction of error information of an ith pipeline stage, setting a magnitude of the input signal according to Formula (I); locking the outputs of all previous-stage comparators in the ipipeline stage of the pipeline analog-to-digital converter; and completing, according to original output code of the pipeline analog-to-digital converter, error extraction by means of adaptive iteration, stage-by-stage, sequentially from a last stage to a first stage of a pipeline. During quantization of error value, the invention performs, by means of a fitting-based adaptive algorithm, foreground extraction of a capacitance mismatch error, a gain bandwidth error, and a kickback error in each stage of the pipeline, without any additional circuit.