The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 31, 2022

Filed:

Aug. 02, 2021
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Shilei Hao, San Diego, CA (US);

Yunliang Zhu, San Diego, CA (US);

Yiwu Tang, San Diego, CA (US);

Dongmin Park, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 23/00 (2006.01); H03K 23/44 (2006.01); H03K 3/356 (2006.01); H03K 21/10 (2006.01); H03K 23/40 (2006.01);
U.S. Cl.
CPC ...
H03K 23/44 (2013.01); H03K 3/356121 (2013.01); H03K 21/10 (2013.01); H03K 23/40 (2013.01);
Abstract

A hybrid true single-phase clock (H-TSPC) circuit includes a first logic circuit comprising non-ratio (NR) logic, a first mode switching device coupled to an output of the first logic circuit, a second logic circuit comprising ratio (R) logic, the second logic circuit configured to receive an output of the first logic circuit, a second mode switching device coupled to an output of the second logic circuit, a third logic circuit comprising non-ratio (NR) logic, the third logic circuit configured to receive an output of the second logic circuit, and a third mode switching device coupled to an output of the third logic circuit, wherein the first logic circuit, second logic circuit, and third logic circuit are configured in a ring.


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