The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 31, 2022

Filed:

Feb. 17, 2021
Applicant:

Te Connectivity Services Gmbh, Schaffhausen, CH;

Inventors:

Christopher William Blackburn, Bothell, WA (US);

John Eugene Westman, Harrisburg, PA (US);

Michael Eugene Shirk, Grantville, PA (US);

Michael David Herring, Apex, NC (US);

Zachary Galbraith, Hummelstown, PA (US);

Assignee:

TE CONNECTIVITY SERVICES GmbH, Schaffhausen, CH;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01R 12/72 (2011.01); H01R 12/57 (2011.01); H01R 13/631 (2006.01); H01R 13/627 (2006.01); H01R 107/00 (2006.01); H01R 24/60 (2011.01); H05K 1/11 (2006.01);
U.S. Cl.
CPC ...
H01R 12/727 (2013.01); H01R 12/57 (2013.01); H01R 12/721 (2013.01); H01R 13/6272 (2013.01); H01R 13/631 (2013.01); H01R 24/60 (2013.01); H01R 2107/00 (2013.01); H05K 1/117 (2013.01);
Abstract

A card edge connector includes a housing having upper and lower card slots receiving upper and lower module circuit cards of a pluggable module. The card edge connector includes a contact assembly having a contact positioner holding upper and lower contacts. A guide feature guides mating of the contact assembly in the housing. A latching feature latchably secures the contact assembly to the housing. The upper contacts are arranged in first and second upper contact arrays. The lower contacts are arranged in first and second lower contact arrays. Contact tails of the upper and lower contacts are positioned at the bottom of the housing for surface mounting to the host circuit board.


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