The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 31, 2022

Filed:

Feb. 18, 2019
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;

Inventors:

Yasutaka Nakazawa, Tochigi, JP;

Kenichi Okazaki, Tochigi, JP;

Takayuki Ohide, Tochigi, JP;

Rai Sato, Tochigi, JP;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/00 (2006.01); H01L 29/00 (2006.01); H01L 29/45 (2006.01); H01L 27/12 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); G02F 1/1368 (2006.01); H01L 27/32 (2006.01);
U.S. Cl.
CPC ...
H01L 29/45 (2013.01); H01L 27/127 (2013.01); H01L 27/1225 (2013.01); H01L 27/1288 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H01L 29/78696 (2013.01); G02F 1/1368 (2013.01); H01L 27/3262 (2013.01);
Abstract

A semiconductor device is fabricated by a method including the following steps: a first step of forming a semiconductor film containing a metal oxide over an insulating layer; a second step of forming a conductive film over the semiconductor film; a third step of forming a first resist mask over the conductive film and etching the conductive film to form a first conductive layer and to expose a top surface of the semiconductor film that is not covered with the first conductive layer; and a fourth step of forming a second resist mask that covers a top surface and a side surface of the first conductive layer and part of the top surface of the semiconductor film and etching the semiconductor film to form a semiconductor layer and to expose a top surface of the insulating layer that is not covered with the semiconductor layer.


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