The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 31, 2022

Filed:

Oct. 08, 2019
Applicant:

Google Llc, Mountain View, CA (US);

Inventors:

Melanie Beauchemin, Mountain View, CA (US);

Madhusudan Iyengar, Foster City, CA (US);

Christopher Malone, Mountain View, CA (US);

Gregory Imwalle, Los Altos, CA (US);

Assignee:

Google LLC, Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/52 (2006.01); H01L 23/38 (2006.01); H01L 25/18 (2006.01); H01L 23/053 (2006.01); H01L 23/433 (2006.01); H01L 25/00 (2006.01); H01L 21/48 (2006.01); F25B 21/02 (2006.01); H01L 23/473 (2006.01);
U.S. Cl.
CPC ...
H01L 23/38 (2013.01); F25B 21/02 (2013.01); H01L 21/4882 (2013.01); H01L 21/52 (2013.01); H01L 23/053 (2013.01); H01L 23/433 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); F25B 2321/023 (2013.01); F25B 2321/0251 (2013.01); H01L 23/473 (2013.01); H01L 2924/1433 (2013.01); H01L 2924/1434 (2013.01);
Abstract

While the use of 2.5D/3D packaging technology results in a compact IC package, it also raises challenges with respect to thermal management. Integrated component packages according to the present disclosure provide a thermal management solution for 2.5D/3D IC packages that include a high-power component integrated with multiple lower-power components. The thermal solution provided by the present disclosure includes a mix of passive cooling by traditional heatsink or cold plate and active cooling by thermoelectric cooling (TEC) elements. Certain methods according to the present disclosure include controlling a temperature during normal operation in an IC package that includes a plurality of lower-power components located adjacent to a high-power component in which the high-power component generates a greater amount of heat relative to each of the lower-power components during normal operation.


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