The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 31, 2022

Filed:

Nov. 30, 2020
Applicant:

Fuji Electric Co., Ltd., Kawasaki, JP;

Inventor:

Naoki Takizawa, Kawasaki, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/12 (2006.01); H01L 23/36 (2006.01); H01L 25/07 (2006.01); H01L 25/18 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/12 (2013.01); H01L 23/36 (2013.01); H01L 25/072 (2013.01); H01L 25/18 (2013.01); H01L 24/48 (2013.01); H01L 2224/48137 (2013.01);
Abstract

A semiconductor device includes an insulating circuit substrate including an insulating plate, a first metal layer formed on a top surface of the insulating plate, and a second metal layer formed on a bottom surface of the insulating plate, a heatsink on whose top surface the insulating circuit substrate is disposed; semiconductor elements disposed on the top surface of the first metal layer through a bonding material, and a case that encloses a perimeter of the insulating circuit substrate and the semiconductor elements. The first metal layer includes circuit patterns electrically connected to the semiconductor elements and an annular pattern formed to enclose the perimeter of the circuit patterns with a gap provided with respect to the circuit patterns. The second metal layer is disposed at a spot that surfaces the annular pattern. The housing is affixed to the annular pattern through an adhesive.


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