The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 31, 2022
Filed:
Aug. 18, 2020
Applicant:
Infineon Technologies Ag, Neubiberg, DE;
Inventor:
Jochen Hilsenbeck, Villach, AT;
Assignee:
Infineon Technologies AG, Neubiberg, DE;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/04 (2006.01); H01L 23/00 (2006.01); H01L 23/482 (2006.01); H01L 29/417 (2006.01); H01L 23/373 (2006.01); H01L 29/40 (2006.01); H01L 29/45 (2006.01); H01L 29/47 (2006.01); H01L 23/367 (2006.01); H01L 29/16 (2006.01);
U.S. Cl.
CPC ...
H01L 21/0485 (2013.01); H01L 23/3736 (2013.01); H01L 23/482 (2013.01); H01L 24/02 (2013.01); H01L 24/05 (2013.01); H01L 29/401 (2013.01); H01L 29/417 (2013.01); H01L 29/41758 (2013.01); H01L 29/45 (2013.01); H01L 29/47 (2013.01); H01L 23/3672 (2013.01); H01L 29/1608 (2013.01); H01L 2224/02166 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/05 (2013.01); H01L 2224/05138 (2013.01); H01L 2224/05647 (2013.01); H01L 2924/10272 (2013.01);
Abstract
A method for manufacturing a semiconductor device includes: providing a semiconductor substrate having first and second sides; forming at least one doping region at the first side; forming a first metallization structure at the first side on and in contact with the at least one doping region; and subsequently forming a second metallization structure at the second side, the second metallization structure forming at least one silicide interface region with the semiconductor substrate and at least one non-silicide interface region with the semiconductor substrate.