The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 31, 2022

Filed:

Aug. 30, 2018
Applicant:

Arm Limited, Cherry Hinton, GB;

Inventors:

Matthew James Horsnell, Cambridge, GB;

Stephan Diestelhorst, Cambridge, GB;

Assignee:

Arm Limited, Cambridge, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/46 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/52 (2006.01);
U.S. Cl.
CPC ...
G06F 9/467 (2013.01); G06F 9/3009 (2013.01); G06F 9/30043 (2013.01); G06F 9/30087 (2013.01); G06F 9/30145 (2013.01); G06F 9/3842 (2013.01); G06F 9/528 (2013.01);
Abstract

In an apparatus () with transactional memory support, a predetermined type of transaction start instruction or a subsequent instruction following the predetermined type of transaction start instruction triggers capture of a lock identifier which identifies a lock variable for controlling exclusive access to at least one resource. In response to a predetermined type of transaction end instruction which follows the predetermined type of transaction start instruction, the lock variable is checked and commitment of results of speculatively executed instructions of the transaction is prevented or deferred when the lock variable indicates that another thread holds the exclusive access to the target resource. This approach can improve performance when executing transactions in a transactional memory based system.


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