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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11345157 B1

PDFFull Text
Date of Patent:
May. 31, 2022

Filed:

Oct. 25, 2019

Logic circuitry package

Applicant:

Hewlett-packard Development Company, L.p., Spring, TX (US);

Inventors:

Sirena Lu, Corvallis, OR (US);

Rogelio Cicili, San Diego, CA (US);

James Michael Gardner, Corvallis, OR (US);

Scott A. Linn, Corvallis, OR (US);

Assignee:

Hewlett-Packard Development Company, L.P., Spring, TX (US);

Attorney:

Dicke, Billig & Czaja, PLLC

Primary Examiner:

Paul R Myers

Int. Cl.
CPC ...
B41J 2/175 (2006.01); B41J 2/045 (2006.01); G06F 13/42 (2006.01); G06F 21/44 (2013.01); G06F 1/12 (2006.01); G06F 1/08 (2006.01); H03K 19/0175 (2006.01); B33Y 30/00 (2015.01); B29C 64/259 (2017.01); G06F 3/12 (2006.01); G01F 23/24 (2006.01); G01F 23/80 (2022.01);
U.S. Cl.
CPC ...
B41J 2/17546 (2013.01); B29C 64/259 (2017.08); B33Y 30/00 (2014.12); B41J 2/0458 (2013.01); B41J 2/04508 (2013.01); B41J 2/04541 (2013.01); B41J 2/04546 (2013.01); B41J 2/04563 (2013.01); B41J 2/04586 (2013.01); B41J 2/1753 (2013.01); B41J 2/17513 (2013.01); B41J 2/17526 (2013.01); B41J 2/17566 (2013.01); G01F 23/247 (2013.01); G01F 23/802 (2022.01); G01F 23/804 (2022.01); G06F 1/08 (2013.01); G06F 1/12 (2013.01); G06F 3/121 (2013.01); G06F 13/4291 (2013.01); G06F 21/44 (2013.01); H03K 19/017509 (2013.01); G06F 13/42 (2013.01); G06F 2213/0016 (2013.01);
Abstract

A logic circuitry package for a replaceable print apparatus component comprises at least one logic circuit and an interface to communicate with a print apparatus logic circuit. The at least one logic circuit is configured to receive, via the interface, calibration parameters including an offset parameter and a sensor ID. The at least one logic circuit is configured to output, via the interface, a digital value corresponding to the sensor ID and offset based on the offset parameter.

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