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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11342625 B1

PDFFull Text
Date of Patent:
May. 24, 2022

Filed:

Nov. 02, 2020

Method of fabricating and method of using porous wafer battery

Applicant:

Xnrgi, Inc., Bothell, WA (US);

Inventors:

Gerard Christopher D'Couto, Edmonds, WA (US);

Slobodan Petrovic, Happy Valley, OR (US);

Assignee:

Xnrgi, Inc., Bothell, WA (US);

Attorney:

Chen-Chi Lin

Primary Examiner:

Michael M Trinh

Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01M 10/04 (2006.01); H01M 10/42 (2006.01); H01M 4/13 (2010.01); H01L 21/768 (2006.01); H01M 50/207 (2021.01); H01M 10/613 (2014.01); H01M 10/615 (2014.01); H01L 21/48 (2006.01); H01L 21/66 (2006.01); H01L 27/088 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01M 4/62 (2006.01); H01M 10/052 (2010.01); H01M 10/0585 (2010.01); H01L 21/60 (2006.01); H01M 4/02 (2006.01);
U.S. Cl.
CPC ...
H01M 50/207 (2021.01); H01L 21/4853 (2013.01); H01L 21/76898 (2013.01); H01L 22/14 (2013.01); H01L 24/11 (2013.01); H01L 24/14 (2013.01); H01L 27/088 (2013.01); H01L 29/66727 (2013.01); H01L 29/7813 (2013.01); H01M 4/13 (2013.01); H01M 4/624 (2013.01); H01M 4/628 (2013.01); H01M 10/0477 (2013.01); H01M 10/052 (2013.01); H01M 10/0585 (2013.01); H01M 10/42 (2013.01); H01M 10/613 (2015.04); H01M 10/615 (2015.04); H01L 2021/60135 (2013.01); H01M 2004/021 (2013.01);
Abstract

A method of fabricating a porous wafer battery comprises the steps of providing a silicon wafer comprising a plurality of pores; applying a first metallization process; applying a passivation process; applying solder balls, aligning the silicon wafer with a substance, and applying a solder reflow process. A method using a porous wafer battery comprises the steps of connecting the porous wafer battery to a plurality of sensors, a plurality of switches, and a battery management system; monitoring temperature, resistance, or current; and electrically disconnecting a non-properly functioning pore.

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