The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 24, 2022

Filed:

Dec. 03, 2019
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventor:

Nao Nagata, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/739 (2006.01); H01L 29/423 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 29/49 (2006.01); H01L 21/308 (2006.01); H01L 21/3065 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7397 (2013.01); H01L 21/3065 (2013.01); H01L 21/3081 (2013.01); H01L 29/0804 (2013.01); H01L 29/0821 (2013.01); H01L 29/1004 (2013.01); H01L 29/1095 (2013.01); H01L 29/41708 (2013.01); H01L 29/4236 (2013.01); H01L 29/42304 (2013.01); H01L 29/4916 (2013.01); H01L 29/6634 (2013.01); H01L 29/66348 (2013.01);
Abstract

A semiconductor device having an IE-type IGBT structure comprises a stripe-shaped trench gate and a stripe-shaped trench emitter arranged to face the trench gate formed in a semiconductor substrate. The semiconductor device further comprises an N-type emitter layer and a P-type base layer both surrounded by the trench gate and the trench emitter formed in the semiconductor substrate. The semiconductor device also comprises a P-type base contact layer arranged on one side of the trench emitter and formed in the semiconductor substrate. The p-type base contact layer, the emitter layer, and the trench emitter are commonly connected with an emitter electrode. The trench emitter is formed deeper than the trench gate in a thickness direction of the semiconductor substrate.


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