The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 24, 2022

Filed:

Oct. 29, 2020
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Digh Hisamoto, Tokyo, JP;

Yoshiyuki Kawashima, Tokyo, JP;

Takashi Hashimoto, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 21/28 (2006.01); H01L 29/10 (2006.01); H01L 29/78 (2006.01); H01L 29/792 (2006.01); H01L 27/11568 (2017.01);
U.S. Cl.
CPC ...
H01L 29/42344 (2013.01); H01L 29/1045 (2013.01); H01L 29/40117 (2019.08); H01L 29/7855 (2013.01); H01L 29/792 (2013.01); H01L 27/11568 (2013.01);
Abstract

A semiconductor device has a split-gate type MONOS structure using a FinFET, and it includes a source and a drain each formed of an n-type impurity diffusion layer, a first channel forming layer which is formed under a control gate and is formed of a semiconductor layer doped with a p-type impurity, and a second channel forming layer which is formed under a memory gate and is formed of a semiconductor layer doped with an n-type impurity. Further, the semiconductor device includes a p-type semiconductor layer which is formed under the second channel forming layer and has an impurity concentration higher than an impurity concentration of a semiconductor substrate.


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