The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 24, 2022

Filed:

Mar. 30, 2018
Applicant:

Sharp Kabushiki Kaisha, Sakai, JP;

Inventors:

Izumi Ishida, Sakai, JP;

Hirohiko Nishiki, Sakai, JP;

Yujiro Takeda, Sakai, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); G09G 3/3258 (2016.01); H01L 27/32 (2006.01);
U.S. Cl.
CPC ...
H01L 27/124 (2013.01); G09G 3/3258 (2013.01); H01L 27/1225 (2013.01); G09G 2300/0809 (2013.01); H01L 27/1288 (2013.01); H01L 27/3262 (2013.01);
Abstract

A display device includes an active matrix substrate, wherein the active matrix substrate is layered with a base insulating film, a first metal layer, a metal oxide layer, a first inorganic insulating film, an oxide semiconductor layer, a second inorganic insulating film, a second metal layer, an interlayer insulating layer, and a third metal layer in order from a lower layer, and the active matrix substrate includes a first transistor configured of a first bottom gate electrode, a top gate electrode, and a source electrode and a drain electrode formed by the third metal layer, the source electrode and the drain electrode are respectively electrically connected to a source region and a drain region of the oxide semiconductor layer, the first bottom gate electrode is overlapped with the oxide semiconductor layer, and a metal of the first metal layer is different from a metal of the metal oxide layer.


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