The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 24, 2022

Filed:

Sep. 15, 2020
Applicant:

Vmware, Inc., Palo Alto, CA (US);

Inventors:

Michael Wei, Santa Clara, CA (US);

Nadav Amit, Mountain View, CA (US);

Amy Tai, Palo Alto, CA (US);

Assignee:

VMWARE, INC., Palo Alto, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/0802 (2016.01); G06F 9/4401 (2018.01);
U.S. Cl.
CPC ...
G06F 12/0802 (2013.01); G06F 9/4406 (2013.01); G06F 2212/68 (2013.01);
Abstract

Techniques for consolidating shared state for translation lookaside buffer (TLB) shootdowns are provided. In one set of embodiments, an operating system (OS) kernel of a computer system can co-locate, in a system memory of the computer system, a plurality of shared data accessed by first and second processing cores of the computer system for performing a translation lookaside buffer (TLB) shootdown of the first processing core by the second processing core, where the co-locating allows the plurality of shared data to occupy a single cache line when brought from the system memory into a CPU (central processing unit) cache of the first or second processing core. This can include, e.g., (1) co-locating a lazy mode indicator and a call function queue (CFQ) head element of the first processing core, such that these two data components occupy the same cache line, and (2) co-locating a TLB flush info entry and a call function data (CFD) entry created by the second processing core at the time of initiating the TLB shootdown, such that these two data components occupy the same cache line.


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