The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 24, 2022

Filed:

Nov. 11, 2020
Applicant:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Inventor:

Tahsin Askar, Austin, TX (US);

Assignee:

ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/0802 (2016.01); G06F 3/06 (2006.01); G06F 1/12 (2006.01); G11C 7/22 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0604 (2013.01); G06F 1/12 (2013.01); G06F 3/0655 (2013.01); G06F 3/0673 (2013.01); G11C 7/222 (2013.01);
Abstract

A shared data transfer clock is used among double data rate memory ranks. A memory controller processes incoming memory access commands destined for at least one of a plurality of double data rate memory ranks and determines when a target DDR memory rank is out of synchronization with respect to the shared data transfer clock and a memory clock. In response to determining that the target DDR memory rank is out of synchronization, the memory controller determines whether the non-target DDR memory rank is out-of-synchronization with respect to the shared data transfer clock and the memory clock, and issues a data transfer clock synchronization command to the target DDR memory rank in response to determining that the non-target DDR memory rank is out-of-synchronization with respect to the shared data transfer clock and the memory clock.


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