The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 24, 2022

Filed:

Apr. 30, 2020
Applicant:

Marvell Asia Pte, Ltd., Singapore, SG;

Inventors:

Avinash Sodani, San Jose, CA (US);

Srinivas Sripada, Roseville, CA (US);

Ramacharan Sundararaman, San Jose, CA (US);

Chia-Hsin Chen, Santa Clara, CA (US);

Nikhil Jayakumar, San Jose, CA (US);

Assignee:

Marvell Asia Pte Ltd, Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/00 (2006.01); G06F 1/26 (2006.01); G06F 1/10 (2006.01); G11C 19/00 (2006.01); H03L 7/08 (2006.01); G06N 20/00 (2019.01); G06F 1/3203 (2019.01);
U.S. Cl.
CPC ...
G06F 1/26 (2013.01); G06F 1/10 (2013.01); G06F 1/3203 (2013.01); G06N 20/00 (2019.01); G11C 19/00 (2013.01); H03L 7/08 (2013.01);
Abstract

A power throttling engine includes a register configured to receive a power throttling signal. The power throttling engine further includes a decoder configured to generate a vector based on a value of the power throttling signal. The value of the power throttling signal is an amount of power throttling of a device. The power throttling engine further includes a clock gating logic configured to receive the vector and further configured to receive a clocking signal. The clock gating logic is configured to remove clock edges of the clocking signal based on the vector to generate a throttled clocking signal.


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