The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 24, 2022
Filed:
Mar. 28, 2019
Applicant:
Google Llc, Mountain View, CA (US);
Inventors:
Shailendra Desai, Ahmedabad, IN;
Mark Pearce, San Francisco, CA (US);
Amit Jain, Ahmedabad, IN;
Jaymin Patel, Ahmedabad, IN;
Assignee:
Google LLC, Mountain View, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/24 (2006.01); G06F 1/32 (2019.01); G06F 15/78 (2006.01); G06F 9/54 (2006.01); G06N 5/04 (2006.01); H04L 9/08 (2006.01); G06F 11/14 (2006.01); G06F 1/324 (2019.01); G06F 1/3234 (2019.01);
U.S. Cl.
CPC ...
G06F 1/24 (2013.01); G06F 1/324 (2013.01); G06F 1/3243 (2013.01); G06F 9/542 (2013.01); G06F 11/1402 (2013.01); G06F 15/7807 (2013.01); G06N 5/043 (2013.01); H04L 9/085 (2013.01);
Abstract
A system for consistently implementing reset and power management of IP agents on a System on a Chip (SoC). When IP agents undergo a reset, an individual negotiation takes placed between an interconnect and each IP agent over a link. Each IP agent can emerge from reset at its own time schedule, independently of the timing of the other IP agents. The interconnect may be configured as a proxy for any IP agent that is inoperable, including prior to reset, when in a power-down mode, or malfunctioning.