The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 17, 2022
Filed:
Apr. 13, 2018
Applicant:
Cirrus Logic International Semiconductor Ltd., Edinburgh, GB;
Inventors:
Marek Sebastian Piechocinski, Edinburgh, GB;
Roberto Brioschi, Austin, TX (US);
Rkia Achehboune, Edinburgh, GB;
Assignee:
Cirrus Logic, Inc., Austin, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B81B 3/00 (2006.01); H04R 19/00 (2006.01); B81C 3/00 (2006.01); H04R 19/04 (2006.01);
U.S. Cl.
CPC ...
H04R 19/005 (2013.01); B81B 3/0021 (2013.01); B81C 3/001 (2013.01); H04R 19/04 (2013.01); B81B 2201/0257 (2013.01); B81B 2203/0127 (2013.01); B81B 2203/033 (2013.01); B81B 2203/0315 (2013.01); B81B 2203/0353 (2013.01); H04R 2201/003 (2013.01);
Abstract
The present disclosure describes techniques for altering the epoxy wettability of a surface of a MEMS device. Particularly applicable to flip-chip bonding arrangements in which a top surface of a MEMS device is adhered to a package substrate. A barrier region is provided on a top surface of the MEMs device, laterally outside a region which forms, or overlies, the backplate and/or the cavity in the transducer substrate. The barrier region comprises a plurality of discontinuities, e.g. dimples, which inhibit the flow of epoxy.