The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 17, 2022
Filed:
Jul. 27, 2020
Applicant:
Kioxia Corporation, Tokyo, JP;
Inventor:
Takuya Haga, Yokohama Kanagawa, JP;
Assignee:
KIOXIA CORPORATION, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/45 (2006.01); G11C 16/34 (2006.01); G11C 29/52 (2006.01); G11C 11/56 (2006.01); G06F 11/10 (2006.01); H03M 13/11 (2006.01); H03M 13/00 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01); G11C 16/16 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
H03M 13/458 (2013.01); G06F 11/1012 (2013.01); G06F 11/1068 (2013.01); G11C 11/5642 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); G11C 16/349 (2013.01); G11C 29/52 (2013.01); H03M 13/1111 (2013.01); H03M 13/45 (2013.01); H03M 13/6325 (2013.01); G11C 16/16 (2013.01); G11C 2029/0411 (2013.01);
Abstract
A memory system includes a nonvolatile semiconductor memory, and a controller configured to maintain a plurality of log likelihood ratio (LLR) tables for correcting data read from the nonvolatile semiconductor memory, determine an order in which the LLR tables are referred to, based on a physical location of a target unit storage region of a read operation, and carry out correcting of data read from the target unit storage region, using one of the LLR tables selected according to the determined order.