The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 17, 2022

Filed:

Jul. 22, 2020
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Kenji Funaoka, Kawasaki Kanagawa, JP;

Takuya Haga, Yokohama Kanagawa, JP;

Toru Katagiri, Sagamihara Kanagawa, JP;

Konosuke Watanabe, Kawasaki Kanagawa, JP;

Assignee:

KIOXIA CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/35 (2006.01); H03M 13/37 (2006.01); G11C 29/52 (2006.01); G06F 11/10 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
H03M 13/356 (2013.01); G06F 11/1048 (2013.01); G06F 11/1068 (2013.01); G11C 29/52 (2013.01); H03M 13/353 (2013.01); H03M 13/3715 (2013.01); G11C 2029/0411 (2013.01);
Abstract

A memory system, which is connectable to a host, includes a non-volatile memory and a controller configured to store data in the non-volatile memory and in a memory region within the host and read the data from the memory region within the host. The controller includes a first encoding/decoding circuit configured to execute encoding/decoding with a first encoding scheme, a second encoding/decoding circuit configured to execute encoding/decoding with a second encoding scheme having a higher error correcting capability than an error correcting capability of the first encoding scheme, an encoding scheme selecting circuit configured to select an encoding/decoding circuit from the first encoding/decoding circuit and the second encoding/decoding circuit to perform encoding of data to be stored in the memory region, based on information about the data read from the memory region.


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