The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 17, 2022

Filed:

Jun. 29, 2020
Applicant:

Xiamen Tianma Micro-electronics Co., Ltd., Xiamen, CN;

Inventors:

Shui He, Xiamen, CN;

Shanshan Zheng, Shanghai, CN;

Yaqi Kuang, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/00 (2006.01); H01L 29/00 (2006.01); H01L 27/12 (2006.01); H01L 29/24 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H01L 27/32 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1225 (2013.01); H01L 27/1251 (2013.01); H01L 27/1255 (2013.01); H01L 27/1259 (2013.01); H01L 29/24 (2013.01); H01L 29/66757 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H01L 29/78633 (2013.01); H01L 29/78648 (2013.01); H01L 29/78675 (2013.01); H01L 29/78696 (2013.01); H01L 27/3262 (2013.01);
Abstract

Array substrate, display panel, display device, and method for forming array substrate are provided. The array substrate includes a substrate and at least one first thin-film transistor on the substrate. the first thin-film transistor includes a first gate electrode; a first gate electrode insulating layer on a side of the first gate electrode facing away from the substrate; a first active layer on a side of the first gate electrode insulating layer facing away from the first gate electrode; a second gate electrode insulating layer on a side of the first active layer facing away from the first gate electrode insulating layer; a second gate electrode on a side of the second gate electrode insulating layer facing away from the first active layer; and a first source electrode and a first drain electrode on the first active layer facing away from the first gate electrode insulating layer.


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