The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 17, 2022

Filed:

Apr. 01, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Yoongoo Kang, Hwaseong-si, KR;

Wonseok Yoo, Seoul, KR;

Hokyun An, Seoul, KR;

Kyungwook Park, Pohang-si, KR;

Dain Lee, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); G11C 5/06 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10814 (2013.01); G11C 5/063 (2013.01); H01L 27/10855 (2013.01); H01L 27/10873 (2013.01); H01L 27/10885 (2013.01); H01L 29/0649 (2013.01);
Abstract

A DRAM device includes an isolation region defining source and drain regions in a substrate, a first bit line structure connected to the source region, a second bit line structure disposed on the isolation region, an inner spacer vertically extending on a first sidewall of the first bit line structure, an air gap is between the inner spacer and an outer spacer, a storage contact between the first and second bit line structures and connected to the drain region, a landing pad structure vertically on the storage contact, and a storage structure vertically on the landing pad structure. The sealing layer seals a top of the first air gap. The sealing layer includes a first sealing layer on a first sidewall of a pad isolation trench, and a second sealing layer on a second sidewall of the pad isolation trench and separated from the first sealing layer.


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