The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 17, 2022

Filed:

Sep. 16, 2020
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Evan Colgan, Montvale, NJ (US);

Timothy J. Chainer, Putnam Valley, NY (US);

Monty Montague Denneau, Putnam, NY (US);

Kai Schleupen, Yorktown Heights, NY (US);

Diego Anzola, Burlington, VT (US);

Mark D. Schultz, Ossining, NY (US);

Layne A. Berge, Rochester, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 23/48 (2006.01); H01L 23/544 (2006.01);
U.S. Cl.
CPC ...
H01L 24/08 (2013.01); H01L 23/481 (2013.01); H01L 23/544 (2013.01); H01L 23/562 (2013.01); H01L 25/0657 (2013.01); H01L 2223/5446 (2013.01); H01L 2224/08145 (2013.01); H01L 2225/06541 (2013.01);
Abstract

A data processing system includes a first wafer comprising a plurality of first chips, and kerf and crack-stop structures around perimeters of the first chips, and a second wafer comprising a plurality second chips, a plurality of interconnect structures through a connection zone between the second chips, and a plurality of thru silicon vias, wherein the first wafer and the second wafer are bonded face-to-face such that the interconnect structures of the second wafer electrically connect adjacent chip sites of the first wafer and where a pitch of the chips on the first and second wafer are equal.


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