The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 17, 2022

Filed:

May. 20, 2020
Applicant:

Virginia Tech Intellectual Properties, Inc., Blacksburg, VA (US);

Inventors:

Jun Wang, Blacksburg, VA (US);

Rolando Burgos, Blacksburg, VA (US);

Dushan Boroyevich, Blacksburg, VA (US);

Joshua Stewart, Blacksburg, VA (US);

Yue Xu, Falls Church, VA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/60 (2006.01); H01L 23/50 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 23/60 (2013.01); H01L 23/50 (2013.01); H01L 23/5227 (2013.01);
Abstract

Various embodiments of laminated planar bus structures that minimize electromagnetic interference (EMI) and parasitic inductance are described. In one embodiment, a laminated planar bus structure may include a plurality of stacked conductive layers and a plurality of stacked insulation layers. The plurality of stacked conductive layers may include positive and negative conductive layers, and conductive ground layers stacked as outer layers as to enclose vertically the positive and the negative conductive layers. In another embodiment, the laminated planar bus structure may include a middle ground layer stacked in between the positive and the negative conductive layers to provide additional reduction in electric field strength. A laminated planar bus structure that is integrated with other power electronics components is also presented.


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