Erase technique for checking integrity of non-data word lines in memory device and corresponding firmware

Abstract

An erase operation for data memory cells is integrated with a process for detecting dummy memory cells and/or select gate transistors which have an out-of-range threshold voltage. In one aspect, an erase operation is performed for the data memory cells of a block followed by a supplementary verify operation for the dummy memory cells and/or select gate transistors. In another aspect, the verify operation occurs during the erase operation and, optionally, also in a supplementary verify operation. A separate pass/fail status can be set for the erase verify of the data memory cells and the verify of the dummy memory cells and/or select gate transistors operations, where the block is assigned to a potential bad block pool or bad block pool based on a status return combination. The out-of-range dummy memory cells and/or select gate transistors can be adjusted by programming or erasing.