The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 17, 2022

Filed:

Mar. 22, 2021
Applicant:

Dxcorr Design Inc., Sunnyvale, CA (US);

Inventors:

Rajesh Tiruvuru, Bangalore, IN;

Manish Agarwal, Fagu, IN;

Nirmalya Ghosh, Fremont, CA (US);

Assignee:

DXCorr Design Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/10 (2006.01); G11C 16/04 (2006.01); G11C 11/16 (2006.01); G11C 13/00 (2006.01); H01L 27/22 (2006.01);
U.S. Cl.
CPC ...
G11C 11/1657 (2013.01); G11C 11/1673 (2013.01); G11C 11/1697 (2013.01); G11C 13/004 (2013.01); H01L 27/228 (2013.01); G11C 2213/79 (2013.01);
Abstract

An electronic biasing circuit for memory operating in a high temperature environment, comprising a first memory cell and a second memory cell, a first MOSFET transistor electrically coupled in series with the first memory cell, wherein the first MOSFET transistor is configured as a switch, a second MOSFET transistor electrically coupled in series with the second memory cell, wherein the second MOSFET transistor is configured as a switch, a DC bias current source configured to generate a negative DC bias voltage signal, a first read/word line electrically coupled to a gate of the first MOSFET transistor, and a second read/word line electrically coupled to a gate of the second MOSFET transistor, wherein in response to a read operation of the first memory cell, the second read/word line is configured to deliver the negative DC bias voltage signal to the gate of the second MOSFET transistor.


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