Cache management circuits for predictive adjustment of cache control policies based on persistent, history-based cache control information

Abstract

A cache management circuit that includes a predictive adjustment circuit configured to predictively generate cache control information based on a cache hit-miss indicator and the retention ranks of accessed cache lines to improve cache efficiency is disclosed. The predictive adjustment circuit stores the cache control information persistently, independent of whether the data remains in cache memory. The stored cache control information is indicative of prior cache access activity for data from a memory address, which is indicative of the data's 'usefulness.' Based on the cache control information, the predictive adjustment circuit controls generation of retention ranks for data in the cache lines when the data is inserted, accessed, and evicted. After the data has been evicted from the cache memory and is later accessed by a subsequent memory request, the persistently stored cache control information corresponding to that memory address increases the information available for determining the usefulness of data.