The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 17, 2022

Filed:

Oct. 14, 2020
Applicant:

Vmware, Inc., Palo Alto, CA (US);

Inventors:

Mazhar Memon, Austin, TX (US);

Zheng Li, Austin, TX (US);

Assignee:

VMware, Inc., Palo Alto, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); G06F 12/14 (2006.01); G06F 21/78 (2013.01); G06F 21/12 (2013.01); G06F 9/455 (2018.01); G06F 9/48 (2006.01); G06F 9/4401 (2018.01); G06F 9/38 (2018.01); G06F 9/30 (2018.01);
U.S. Cl.
CPC ...
G06F 12/023 (2013.01); G06F 9/4411 (2013.01); G06F 9/45558 (2013.01); G06F 9/4881 (2013.01); G06F 12/1408 (2013.01); G06F 21/126 (2013.01); G06F 21/78 (2013.01); G06F 9/3004 (2013.01); G06F 9/3877 (2013.01); G06F 2009/45583 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/1052 (2013.01);
Abstract

At least one application runs on a hardware platform that includes a plurality of coprocessors, each of which has a respective internal memory space. An intermediate software layer (MVL) is transparent to the application and intercepts calls for coprocessor use. If the data corresponding to an application's call, or separate calls from different entities (including different applications) to the same coprocessor, to the API of a target coprocessor, cannot be stored within the available internal memory space of the target coprocessor, but comprises data subsets that individually can, the MVL intercepts the call response to the application/entities and indicates that the target coprocessor can handle the request. The MVL then transfers the data subsets to the target coprocessor as needed by the corresponding kernel(s) and swaps out each data subset to the internal memory of another coprocessor to make room for subsequently needed data subsets.


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