The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 17, 2022

Filed:

Jun. 23, 2020
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Chi-Lin Hsu, San Jose, CA (US);

Tai-Yuan Tseng, Milpitas, CA (US);

Yan Li, Milpitas, CA (US);

Hiroyuki Mizukoshi, Kawasaki, JP;

Assignee:

SanDisk Technologies LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G11C 11/00 (2006.01); G11C 5/06 (2006.01); G11C 11/4072 (2006.01); G06F 8/65 (2018.01); G11C 29/16 (2006.01); G11C 5/14 (2006.01); G11C 16/28 (2006.01); G11C 11/56 (2006.01); G11C 29/46 (2006.01); G11C 16/34 (2006.01); G11C 16/24 (2006.01); G11C 16/10 (2006.01); G11C 16/08 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0679 (2013.01); G06F 8/65 (2013.01); G06F 9/3004 (2013.01); G06F 9/30185 (2013.01); G06F 9/3879 (2013.01); G11C 5/063 (2013.01); G11C 5/145 (2013.01); G11C 11/005 (2013.01); G11C 11/4072 (2013.01); G11C 11/5628 (2013.01); G11C 11/5642 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/24 (2013.01); G11C 16/28 (2013.01); G11C 16/349 (2013.01); G11C 16/3459 (2013.01); G11C 29/16 (2013.01); G11C 29/46 (2013.01); G06F 2212/2022 (2013.01); G11C 2211/5634 (2013.01);
Abstract

A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The control circuit includes a programmable and reprogrammable microcontroller. The microcontroller has a first processor that executes instructions to coordinate sequences of voltages applied to the memory structure by a first circuit in order to perform memory operations. The microcontroller has a second processor that executes second instructions to control a second circuit to test conditions of the non-volatile memory cells in response to the voltages applied to the memory structure. The microcontroller may have a third processor that controls the flow of the memory operation and directs the first and second processors to execute the instructions. The instructions of the various processors may be updated, which provides for flexible flow, core operation control, and condition testing.


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