The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 17, 2022

Filed:

Mar. 31, 2020
Applicant:

Nxp B.v., Eindhoven, NL;

Inventor:

Jo Frisson, Hoegaarden, BE;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G11C 7/22 (2006.01); G06F 13/28 (2006.01); G06F 1/10 (2006.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0659 (2013.01); G06F 1/10 (2013.01); G06F 3/0604 (2013.01); G06F 3/0673 (2013.01); G06F 13/1668 (2013.01); G06F 13/28 (2013.01); G11C 7/22 (2013.01);
Abstract

Embodiments of a method and device are disclosed. In an embodiment, a controller includes a plurality of memories each having registers that are accessible using an address, a plurality of memory controllers each coupled to a memory and configured to control read and write operations to the respective coupled memory, a bus coupled to each of the memory controllers configured to communicate data and commands to each of the memory controllers, a plurality of processing cores coupled to the bus and configured to read and write data to the memories through the memory controllers, and a plurality of isolation stages, each isolation stage being coupled between a memory controller and a memory and configured to isolate the respective memory from receiving a memory clock signal when the memory is not addressed by the memory controller.


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