The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 17, 2022

Filed:

Jan. 29, 2021
Applicant:

Marvell Asia Pte, Ltd., Singapore, SG;

Inventors:

Ramacharan Sundararaman, San Jose, CA (US);

Nithyananda Miyar, San Jose, CA (US);

Hakseon Lee, Kanata, CA;

Assignee:

Marvell Asia Pte Ltd, Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0622 (2013.01); G06F 3/0644 (2013.01); G06F 3/0679 (2013.01);
Abstract

A new approach is proposed to support hardware-based memory region protection for an electronic device. One or more sources/requesting access to a memory/storage that is local to or associated with the electronic device are categorized into at least two types—a set of trusted sources and a set of untrusted sources. Accordingly, a memory manager is configured to partition the memory into a plurality of regions including at least a secure region that is accessible only by a trusted source and a non-secure region that is accessible by an untrusted source. Any access attempt to the secure region by one of the untrusted sources will be blocked. During operation, the memory manager is configured to dynamically adjust the demarcation and/or size of the secure region and the non-secure region of the memory via remapping of the memory based on current access need to data maintained in the memory.


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