The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 17, 2022

Filed:

Jun. 04, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventor:

Seung-Bum Kim, Hwaseong-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G11C 16/30 (2006.01); G11C 5/14 (2006.01); H01L 27/1157 (2017.01); H01L 27/11565 (2017.01); G06F 11/10 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01); G11C 29/52 (2006.01); G11C 29/04 (2006.01); G11C 29/12 (2006.01); H01L 27/11582 (2017.01);
U.S. Cl.
CPC ...
G06F 3/0616 (2013.01); G06F 3/0604 (2013.01); G06F 3/0619 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 11/1068 (2013.01); G11C 5/143 (2013.01); G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01); G11C 29/52 (2013.01); H01L 27/1157 (2013.01); H01L 27/11565 (2013.01); G11C 2029/0409 (2013.01); G11C 2029/1206 (2013.01); H01L 27/11582 (2013.01);
Abstract

Nonvolatile memory device includes a memory cell array and a control circuit. The memory cell array includes a plurality of memory blocks, the memory blocks including a plurality of memory cells coupled to word-lines respectively, the word-lines are stacked vertically on a substrate, and some memory cells of the plurality of memory cells are selected by sub-block unit smaller than one memory block. The control circuit divides sub-blocks of a first memory block into at least one bad sub-block and at least one normal sub-block based on error occurrence frequency of each of the sub-blocks, and applies different program/erase cycles to the at least one bad sub-block and the at least one normal sub-block based on a command and an address provided from external to the nonvolatile memory device. The at least one bad sub-block and the at least one normal sub-block are adjacent each other.


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