The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 17, 2022
Filed:
Dec. 05, 2019
Texas Instruments Incorporated, Dallas, TX (US);
Khushboo Agarwal, Bangalore, IN;
Sanjay Krishna Hulical Vijayaraghavachar, Karnataka, IN;
Raashid Moin Shaikh, Bangalore, IN;
Srivaths Ravi, Bangalore, IN;
Wilson Pradeep, Bangalore, IN;
Rajesh Kumar Tiwari, Bangalore, IN;
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Abstract
Methods for testing an application specific integrated circuit (ASIC). A set of representations is created that overlays power density information and clock gate physical locations of a set of clock gates in a critical sub-chip of the ASIC for test mode power analysis. The set of representations are further grouped in the sub-chip into various groups based on overlapping of the set of representations. Then, a set of test control signals is generated corresponding to each of the set of clock gates during at-speed test mode of operation such that each clock gate with overlapping representations receive different test control signals. Further, patterns are generated using a virtual constraint function to selectively enable the set of test control signals such that the set of test control signals are not activated simultaneously.