Analog delay lines and analog readout systems

Abstract

An analog delay line includes a clock generator, an analog sampling circuit, a bank of analog memory cells, a memory controller, an analog readout circuit, and an analog multiplexer. The clock generator is configured to output plural reception clock signals of different frequencies and plural transmission clock signals of different frequencies, the transmission clock signals offset in accumulated phase relative to the reception clock signals. The analog sampling circuit is controlled by at least one of the reception clock signals, and is configured to output a sequence of sampled voltages of an analog input signal. The memory controller is configured to control a write operation at a write frequency of at least one of the reception clock signals and a read operation at a read frequency of at least one of the transmission clock signals. The write operation is for sequentially storing the sampled voltages received from the analog sampling circuit in the bank of analog memory cells, and the read operation is for sequentially reading the sampled voltages from the bank of analog memory cells. The analog readout circuit is configured to buffer the sampled voltages read from the bank of analog memory cells. The analog multiplexer is controlled by at least one of the transmission clock signals, and is configured to multiplex the sampled voltages buffered by the readout circuit to generate an analog output signal. A sampling rate of the analog input signal is within a factor of 2 of a sampling rate of the analog output signal.