The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 10, 2022

Filed:

Apr. 02, 2020
Applicant:

Cryptography Research, Inc, Sunnyvale, CA (US);

Inventors:

Scott C. Best, Palo Alto, CA (US);

Ming Li, Fremont, CA (US);

Gary B. Bronner, Los Altos, CA (US);

Mark Evan Marson, Carlsbad, CA (US);

Assignee:

Cryptography Research, Inc., San Francisco, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/573 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/73215 (2013.01); H01L 2224/73253 (2013.01);
Abstract

An anti-tamper layer is applied to a blank wafer. The layered wafer is then diced into shield dies. A shield die is oxide-to-oxide bonded to the top of an active die such that removing the shield die will damage the active die. The shield die may be sized and positioned such that wirebond pads along one or more edges of the active die remain exposed. The exposed wirebond pads may be used to electrically connect, via wirebonds, the active die to a substrate. A second shield die may be attached to the bottom of the active die to help protect against the use of bottom-to-top delayering.


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