The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 10, 2022

Filed:

Nov. 26, 2019
Applicant:

Fraunhofer-gesellschaft Zur Foerderung Der Angewandten Forschung E.v., Munich, DE;

Inventors:

Ivan Ndip, Berlin, DE;

Tanja Braun, Berlin, DE;

Klaus-Dieter Lang, Berlin, DE;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 23/66 (2006.01); H01Q 1/22 (2006.01); H01L 23/00 (2006.01); H01Q 1/52 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5225 (2013.01); H01L 23/5227 (2013.01); H01L 23/66 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01Q 1/2283 (2013.01); H01Q 1/521 (2013.01); H01L 2223/6677 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/15311 (2013.01);
Abstract

A wafer-level packaging based module includes an antenna board and a chip board. The antenna board includes at least one antenna layer with introduced antenna element and a shielding layer with introduced shielding element in the area of the at least one antenna element opposite to the antenna layer. The chip board includes a contacting layer, a rewiring layer opposite to the contacting layer and the shielding layer having at least one shielding element arranged on the rewiring layer. A chip layer having at least one chip is arranged between the contacting layer and the rewiring layer. Further, the chip layer includes at least one via connecting the contacting layer to the rewiring layer.


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