The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 10, 2022

Filed:

Jul. 29, 2019
Applicant:

Qromis, Inc., Santa Clara, CA (US);

Inventors:

Vladimir Odnoblyudov, Danville, CA (US);

Cem Basceri, Los Gatos, CA (US);

Shari Farrens, Boise, ID (US);

Ozgur Aktas, Pleasanton, CA (US);

Assignee:

QROMIS, INC., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); C30B 29/40 (2006.01); H01L 21/8252 (2006.01); H01L 21/8238 (2006.01); H01L 29/20 (2006.01); H01L 29/16 (2006.01); H01L 27/06 (2006.01); H01L 27/092 (2006.01); H01L 23/522 (2006.01); C30B 25/18 (2006.01); C30B 29/06 (2006.01); H01L 21/8258 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 21/0242 (2013.01); C30B 25/18 (2013.01); C30B 29/06 (2013.01); C30B 29/406 (2013.01); H01L 21/0243 (2013.01); H01L 21/0245 (2013.01); H01L 21/0254 (2013.01); H01L 21/02458 (2013.01); H01L 21/02488 (2013.01); H01L 21/02505 (2013.01); H01L 21/02516 (2013.01); H01L 21/02639 (2013.01); H01L 21/8252 (2013.01); H01L 21/8258 (2013.01); H01L 21/823871 (2013.01); H01L 23/5221 (2013.01); H01L 27/0605 (2013.01); H01L 27/0617 (2013.01); H01L 27/092 (2013.01); H01L 29/16 (2013.01); H01L 29/2003 (2013.01); H01L 21/02532 (2013.01); H01L 21/76254 (2013.01);
Abstract

A method of fabricating a semiconductor structure includes providing an engineered substrate including a polycrystalline substrate, a barrier layer encapsulating the polycrystalline substrate, and a bonding layer coupled to the barrier layer. The method further includes forming a first silicon layer coupled to the bonding layer, forming a dielectric layer coupled to the first silicon layer, forming a second silicon layer coupled to the dielectric layer, removing a portion of the second silicon layer and a corresponding portion of the dielectric layer to expose a portion of the first silicon layer, forming a gallium nitride (GaN) layer coupled to the exposed portion of the first silicon layer, forming a gallium nitride (GaN) based device coupled to the GaN layer, and forming a silicon-based device coupled to a remaining portion of the second silicon layer.


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