The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 10, 2022

Filed:

Jul. 09, 2020
Applicant:

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Inventors:

Gianbattista Lo Giudice, Pedara, IT;

Giovanni Matranga, Catania, IT;

Rosario Roberto Grasso, S. Agata Li Battiati, IT;

Alberto Jose' Di Martino, Palagonia, IT;

Assignee:

STMICROELECTRONICS S.R.L., Agrate Brianza, IT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/14 (2006.01); G06F 3/06 (2006.01); G11C 16/34 (2006.01); G11C 16/26 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 16/14 (2013.01); G06F 3/0616 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 16/0408 (2013.01); G11C 16/26 (2013.01); G11C 16/3445 (2013.01); G11C 16/3495 (2013.01);
Abstract

A method of operating a non-volatile memory including having a first set of non-volatile memory cells and a second set of non-volatile memory cells. The first set of non-volatile memory cells and second set of non-volatile memory cells are associated with host addresses. Voltage levels are determined to erase the first and second sets of non-volatile memory cells. The first and second sets of non-volatile memory cells are disassociated from the host addresses. And, the first set of non-volatile memory cells is associated to another address based on the voltage level effective to erase the non-volatile memory cells.


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