The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 10, 2022

Filed:

Jul. 31, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jaehyung Lee, Hwaseong-si, KR;

JungSik Kim, Seoul, KR;

Youngdae Lee, Yongin-si, KR;

Duyeul Kim, Hwaseong-si, KR;

Sungmin Yim, Suwon-si, KR;

Kwangil Park, Yongin-si, KR;

Chulsung Park, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/4072 (2006.01); G11C 5/04 (2006.01); H01L 25/065 (2006.01); G11C 11/408 (2006.01); G11C 11/409 (2006.01); H01L 23/498 (2006.01); G11C 29/02 (2006.01); G11C 29/50 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4072 (2013.01); G11C 5/04 (2013.01); G11C 11/408 (2013.01); G11C 11/409 (2013.01); G11C 29/022 (2013.01); G11C 29/028 (2013.01); G11C 29/50008 (2013.01); H01L 23/49838 (2013.01); H01L 25/0655 (2013.01); G11C 7/109 (2013.01); G11C 7/1063 (2013.01); G11C 7/1075 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A semiconductor device includes a first die connected to a first channel, the first die comprising a first memory chip; and a second die connected to a second channel, the second die comprising a second memory chip, the first and second channels being independent of each other and a storage capacity and a physical size of the second die being the same as those of the first die. The first and second dies are disposed in one package, and the package includes an interconnection circuit disposed between the first die and the second die to transfer signals between the first memory chip and the second memory chip.


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