The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 10, 2022

Filed:

Apr. 09, 2021
Applicant:

Sharp Kabushiki Kaisha, Sakai, JP;

Inventors:

Yasuaki Iwase, Sakai, JP;

Takuya Watanabe, Sakai, JP;

Akira Tagawa, Sakai, JP;

Jun Nishimura, Sakai, JP;

Yohei Takeuchi, Sakai, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G 3/36 (2006.01); G11C 19/28 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3677 (2013.01); G09G 3/3696 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/0291 (2013.01); G09G 2310/08 (2013.01); G11C 19/28 (2013.01);
Abstract

A gate driver is constituted of a first gate driver including a first shift register that is configured by bistable circuits corresponding to gate bus lines on odd-numbered lines arranged on one side of a display portion, and a second gate driver including a second shift register that is configured by bistable circuits corresponding to gate bus lines on even-numbered lines arranged on another side of the display portion. A first buffer circuit is provided on one end side of each gate bus line, and a second buffer circuit is provided on another end side of each gate bus line. A control signal for controlling the scanning order of the gate bus line is given to the bistable circuit and the second buffer circuit.


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