The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 10, 2022

Filed:

May. 06, 2021
Applicant:

Samsung Display Co., Ltd., Yongin-si, KR;

Inventors:

Jun-Hyun Park, Suwon-si, KR;

Young-Wan Seo, Suwon-si, KR;

An-Su Lee, Seoul, KR;

Bo-Yong Chung, Suwon-si, KR;

Kang-Moon Jo, Hwaseong-si, KR;

Chong-Chul Chai, Seoul, KR;

Assignee:

SAMSUNG DISPLAY CO., LTD., Yongin-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/3233 (2016.01); H01L 51/52 (2006.01); G09G 3/3258 (2016.01); H01L 27/32 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3233 (2013.01); G09G 3/3258 (2013.01); H01L 51/5203 (2013.01); G09G 2300/0814 (2013.01); G09G 2300/0819 (2013.01); G09G 2310/0264 (2013.01); G09G 2320/0223 (2013.01); G09G 2320/0233 (2013.01); H01L 27/3265 (2013.01);
Abstract

A display panel driver drives pixels based on first power having at least three voltage levels, second power having a constant voltage, and third power having two voltage levels. Each pixel includes a first transistor connected between first and second nodes and including a gate electrode to receive a scan signal, a second transistor connected between the second node and a third node in series with the first transistor and including a gate electrode to receive the third power, and a driving transistor connected between a source of the first power and the third node and including a gate electrode connected to the first electrode to control a driving current for an organic light emitting diode. A first capacitor is connected between a source of the third power and the first node, and a second capacitor is connected between the second node and one of the data lines.


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