The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 10, 2022

Filed:

Aug. 27, 2019
Applicant:

Cerebras Systems Inc., Sunnyvale, CA (US);

Inventors:

Sean Lie, Los Gatos, CA (US);

Michael Edwin James, San Carlos, CA (US);

Michael Morrison, Sunnyvale, CA (US);

Srikanth Arekapudi, Los Altos Hills, CA (US);

Gary R. Lauterbach, Los Altos, CA (US);

Assignee:

Cerebras Systems Inc., Sunnyvale, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06N 3/063 (2006.01); G06F 11/14 (2006.01); G06N 3/04 (2006.01); G06N 3/08 (2006.01);
U.S. Cl.
CPC ...
G06N 3/063 (2013.01); G06F 11/14 (2013.01); G06N 3/0472 (2013.01); G06N 3/08 (2013.01);
Abstract

Techniques in advanced deep learning provide improvements in one or more of cost, accuracy, performance, and energy efficiency. The deep learning accelerator is implemented at least in part via wafer-scale integration. The wafer comprises a plurality of processor elements, each augmented with redundancy-enabling couplings. The redundancy-enabling couplings enable using redundant ones of the processor elements to replace defective ones of the processor elements. Defect information gathered at wafer test and/or in-situ, such as in a datacenter, is used to determine configuration information for the redundancy-enabling couplings.


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