The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 10, 2022

Filed:

Jul. 20, 2020
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Ygal Arbel, Morgan Hill, CA (US);

Sagheer Ahmad, Cuptertino, CA (US);

Gaurav Singh, Los Altos, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/1027 (2016.01); H03K 19/1776 (2020.01);
U.S. Cl.
CPC ...
G06F 12/1027 (2013.01); H03K 19/1776 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/68 (2013.01);
Abstract

An example programmable integrated circuit (IC) includes a processing system having a processor, a master circuit, and a system memory management unit (SMMU). The SMMU includes a first translation buffer unit (TBU) coupled to the master circuit, an address translation (AT) circuit, an AT interface coupled to the AT circuit, and a second TBU coupled to the AT circuit, and programmable logic coupled to the AT circuit in the SMMU through the AT interface.


Find Patent Forward Citations

Quick Actions:

Arbel, Ygal. (2022). Hardware-based virtual-to-physical address translation for programmable logic masters in a system on chip (U.S. Patent No. 11327899). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11327899

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…