The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 10, 2022

Filed:

May. 20, 2020
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Duck Hoi Koo, Suwon-si, KR;

Gun Woo Yeon, Icheon-si, KR;

Young Ho Kim, Seongnam-si, KR;

Seung Geol Baek, Seongnam-si, KR;

Suk Ho Jung, Seongnam-si, KR;

Assignee:

SKhynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/02 (2006.01); G06F 12/0871 (2016.01); G06F 9/54 (2006.01); G06F 12/0873 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0246 (2013.01); G06F 9/544 (2013.01); G06F 12/0871 (2013.01); G06F 12/0873 (2013.01); G06F 2212/7201 (2013.01); G06F 2212/7204 (2013.01);
Abstract

There are provided a controller and a memory system having the controller. The controller includes: a first storage area configured to store mapping information between logical addresses of logical regions of a storage device coupled to the controller and physical addresses of memory blocks of the storage device, the logical regions being divided into logical units including a first logical unit; and a second storage area configured to store allocation information on logical addresses of logical regions allocated to the first logical unit, each of the logical regions allocated to the first logical unit having a corresponding index, wherein the second storage area is further configured to store a location table for the first logical unit that includes index information having a smallest index corresponding to a logical region allocated to the first logical unit without having other indices corresponding to remaining logical regions allocated to the first logical unit and number information on a total number of the logical regions allocated to the first logical unit.


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